1. Field of the Invention
The present invention is related to the refreshing of a dynamic random access memory (DRAM), and specifically to a refreshing system in which memory banks may be refreshed continuously, even after a failure has been detected in a portion of the refresh logic.
2. General Discussion of the Background Art
Prior DRAM refresh systems have been arranged into pairs of banks, and refresh logic has been employed to refresh each of the banks through separate logic channels. In each of the logic channels there was circuitry to verify the correct operation of the refresh timing circuit associated with that particular bank, or pairs of banks. When a refresh error was detected in one refresh section that serviced one set of banks, these memory banks could shut down and operation could be continued with the remaining pairs of banks, but with a consequent reduction in memory capacity.
In the present invention, the entire memory system is considered as a unitary structure with regard to the refresh mechanism. A plurality of refresh channels are still employed. However, when a failure has been detected in one of the channels, refreshing of the entire memory continues through the other channels, while the detected error allows for replacement of the circuitry associated with the failed channel.